ARIZONA MICROTEK, INC.
AZ10E111
AZ100E111
ECL/PECL 1:9 Differential Clock Driver
FEATURES
PACKAGE AVAILABILITY
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Low Skew
Differential Design
Clock Enable
VBB Output
Operating Range of 4.2V to 5.46V
75kΩ Internal Input Pulldown Resistors
Direct Replacement for ON Semi
MC10E111 & MC100E111
PACKAGE
PART NUMBER
MARKING
NOTES
AZM10E111
<Date Code>
AZM100E111
<Date Code>
PLCC 28
AZ10E111FN
1,2
PLCC 28
AZ100E111FN
1,2
1
2
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
Date code format: “YY” for year followed by “WW” for week.
DESCRIPTION
The AZ10/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN
signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the
device by forcing all Q outputs LOW and all Qˉ outputs HIGH.
The AZ100E111 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the VBB reference should be connected to one side of the IN/IˉNˉ
differential input pair. The input signal is then fed to the other IN/IˉNˉ input. The VBB pin should be used only as a
bias for the E111 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a
0.01μF capacitor.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and
layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process
control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, low skew device.
To ensure that the tight skew specification is met, both sides of the differential output must be terminated into
50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on
the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of
the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 ? MESA, ARIZONA 85204 ? USA ? (480) 962-5881 ? FAX (480) 890-2541
www.azmicrotek.com
AZM [ ARIZONA MICROTEK, INC ]
