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AZ100LVEL16NG 參數 Datasheet PDF下載

AZ100LVEL16NG圖片預覽
型號: AZ100LVEL16NG
PDF下載: 下載PDF文件 查看貨源
內容描述: ECL / PECL差分接收器 [ECL/PECL Differential Receiver]
分類和應用:
文件頁數/大小: 7 頁 / 82 K
品牌: AZM [ ARIZONA MICROTEK, INC ]
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ARIZONA MICROTEK, INC.  
AZ10LVEL16  
AZ100LVEL16  
ECL/PECL Differential Receiver  
PACKAGE AVAILABILITY  
FEATURES  
PACKAGE  
PART NUMBER MARKING NOTES  
?
Green and RoHS Compliant / Lead (Pb)  
Free Packages available  
250ps Propagation Delay  
High Bandwidth Output Transitions  
Operating Range of 3.0V to 5.5V  
Internal Input Pulldown Resistors  
Direct Replacement For ON  
Semiconductor MC10EL16, MC100EL16,  
& MC100LVEL16  
AZM10  
SOIC 8  
AZ10LVEL16D  
1,2  
LVEL16  
AZM100  
LVEL16  
?
?
?
?
?
SOIC 8  
AZ100LVEL16D  
1,2  
SOIC 8 RoHS  
Compliant / Lead  
(Pb) Free  
AZM100+  
LVEL16  
AZ100LVEL16D+  
AZ10LVEL16T  
1,2  
1,2  
1,2  
1,2  
1,2  
AZT  
LV16  
TSSOP 8  
TSSOP 8 RoHS  
Compliant / Lead  
(Pb) Free  
?
IBIS Model Files Available on Arizona  
Microtek Website  
AZT+  
LV16  
AZ10LVEL16T+  
AZ100LVEL16T  
AZ100LVEL16T+  
AZH  
LV16  
TSSOP 8  
TSSOP 8 RoHS  
Compliant / Lead  
(Pb) Free  
AZH+  
LV16  
DESCRIPTION  
MLP 8 (2x2)  
Green / RoHS  
Compliant / Lead  
(Pb) Free  
The AZ10/100LVEL16 is a differential  
receiver. The device is functionally equivalent  
to the E116 device with higher performance  
capabilities. With output transition times  
significantly faster than the E116, the LVEL16  
is ideally suited for interfacing with high  
frequency sources.  
Q6G  
<Date Code>  
AZ100LVEL16NG  
1,3  
1
2
3
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)  
Tape & Reel.  
Date code format: “Y” or “YY” for year followed by “WW” for week on  
underside of part.  
Date code format: “Y” for year followed by “WW” for week.  
The LVEL16 provides a VBB output for  
single-ended use or a DC bias reference for AC coupling to the device. For single-ended input applications, the VBB  
reference should be connected to one side of the D/Dˉ differential input pair. The input signal is then fed to the other  
D/Dˉ input. The VBB pin can support 1.5 mA sink/source current. When used, the VBB pin should be bypassed to  
ground via a 0.01 μF capacitor.  
Under open input conditions internal input clamps will force the Q output LOW.  
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.  
PINOUT ASSIGNMENT  
PIN DESCRIPTION  
PIN  
D, Dˉ  
Q, Qˉ  
VBB  
VCC  
VEE  
NC  
FUNCTION  
Data Inputs  
Data Outputs  
Reference Voltage Output  
Positive Supply  
Negative Supply  
No Connect  
1
2
3
4
8
VCC  
NC  
Q
7
6
5
D
D
Q
VEE  
VBB  
1630 S. STAPLEY DR., SUITE 127 ? MESA, ARIZONA 85204 ? USA ? (480) 962-5881 ? FAX (480) 890-2541  
www.azmicrotek.com  
 復制成功!